Shanghai UniVista Industrial Software Group, an electronic design automation (EDA) and industrial software solutions provider, announced on Wednesday that it has completed a pre-A round of financing exceeding 1.1 billion yuan ($164.3 million).
This round featured joint investment from Shangqi Capital, IDG, CAS Investment Management Co., Ltd., China Automotive Chip Alliance, Feixiang Capital, Guangzhou Automobile GAC Capital Co., Ltd., and other well-known institutions. Existing shareholders SummitView Capital and Mulan Investment also participated in this round, while Taihecap acted as the exclusive financial consultant. UniVista has now completed two rounds of financing, garnering a cumulative amount of nearly 3 billion yuan.
Founded in 2020, UniVista is an independent provider of high-performance industrial software solutions. Its initial focus was on EDA, and it is committed to helping semiconductor enterprises solve severe challenges and key problems in innovation and development.
UniVista has launched several EDA products and solutions recently, which can help to better address the challenges of different tasks such as functional verification, debugging and large-scale test management in chip development, as well as advanced packaging system-level design collaboration.
The EDA products and solutions released by the firm include: UniVista Advanced Prototyping System (“UV APS”), a next-generation timing-driven high-performance prototyping system. UV APS is a prototyping system that rapidly automates high-performance prototyping of 4-100 VU19P FPGA cascades. Additionally, there is the sign-off full-featured version of UniVista Integrator (“UVI”), an advanced packaging collaborative design inspection tool.
The company has also released the UniVista Debugger (“UVD”), a high-efficiency and easy-to-use digital function simulation debugging tool, UniVista Verification Productivity System (“VPS”), a large-scale function verification regression test management platform, and UniVista Hybrid IPK (“HIPK”), a plug-and-play hybrid prototype system-level IP verification scheme.